1. Field of the Invention
The present invention relates to a semiconductor memory apparatus, e.g., a dynamic RAM (DRAM) and, more particularly, to a method of driving a word line.
2. Description of the Related Art
A semiconductor memory generally comprises a block which is constituted by regularly repetitive identical patterns such as memory cells and a block which is constituted by irregularly repetitive patterns such as peripheral circuits for accessing the memory cells.
FIG. 2 shows the layout of a DRAM. Memory cell arrays 22a, 22b, 22c, and 22d constituted by regularly repetitive patterns are arranged at the central portion of a semiconductor chip 21. A peripheral circuit 23 constituted by irregularly repetitive patterns is arranged between the memory cell arrays 22a and 22b and the memory cell arrays 22c and 22d. In addition, a peripheral circuit 24a including a row decoder (to be referred to as an "RDC" hereinafter) is arranged between the memory cell arrays 22a and 22b, and a peripheral circuit 24b including an RDC is arranged between the memory cell arrays 22c and 22d. In this DRAM, the peripheral circuit 24a including the RDC is commonly used for the adjacent memory cell arrays 22a and 22b, and the peripheral circuit 24b is commonly used for the adjacent memory cell arrays 22c and 22d.
In addition, peripheral circuits 25 each including a column decoder are arranged between the peripheral circuit 23 and the memory cell arrays 22a and 22d, respectively. In addition, bonding pads (not shown), an input protecting circuit therefor, and a peripheral circuit 29 constituted by irregularly repetitive patterns are arranged at the peripheral portion of the semiconductor chip 21.
Each of the memory cell arrays 22a to 22b is divided into 2.sup.n or 2n (n is a natural number) areas as indicated by dotted lines, and each area partitioned by the dotted lines constitutes a minimum memory cell array MCAmin. Referring to FIG. 2, each of the memory cell arrays 22a to 22d is divided into 8 areas and has 8 minimum memory cell arrays MCAmin. A plurality of word lines (WL) 26 are arranged in each memory cell array MCAmin in the row direction, and a plurality of bit lines (BL) 27 are arranged in each memory cell array MCAmin in the column direction. A plurality of column selection lines (CSL) connected to the column decoder are arranged on the area of the memory cell arrays in parallel to the bit lines 27.
In order to understand a bit image from a pattern layout, assume that the chip layout shown in FIG. 2 has a 16-Mbit capacity. FIG. 3 is a map obtained by expressing the chip layout in FIG. 2 as a physical image.
The 4096 word lines 26 are arranged in each of the memory cell arrays 22a to 22d in the row direction. Therefore, 512 word lines are present in each minimum memory cell array MCAmin. On the other hand, bit lines, more accurately, 1024 pairs of bit lines, are arranged in each of the memory cell arrays 22a to 22d in the column direction. Since memory cells are respectively arranged on intersections between the word lines and the bit lines, it is understood that the memory cells have a 16-Mbit capacity.
An actual process of selecting a word line to access data will be described below. When simple read or write access is to be performed, one word line is selected, and data may be accessed from the bit lines crossing the selected word line. However, since a refresh operation is required for a DRAM, it is not necessarily. satisfied that only one word line is selected.
Therefore, a memory cell of the DRAM is shown in FIG. 4, and the operation of the memory cell will be described below. A memory cell of the DRAM is generally constituted by a selection transistor 41 and a capacitor 42, a small charge corresponding to storage data is accumulated and held in a storage node 43 of the capacitor 42. However, leakage necessarily occurs in the capacitor 42. As this leakage, junction leakage which allows charges to flow into a substrate or capacitor insulating film leakage which allows charges to flow into a capacitor electrode 44 is known. Therefore, in order to hold data holding properties, in other words, in order to avoid the leakage, the refresh operation described above must be periodically performed.
This refresh operation is performed for all the memory cells in 512 refresh cycles/8 msec for, a 1 Mbit, and in 1024 refresh cycles/16 msec for, e.g., 16 Mbit depending on an external specification. In the example as described above, since the memory cells have a 16-Mbit capacity, when a refresh operation is performed in 2048 refresh cycles/32 msec, as shown in FIG. 5, at least four word lines 51 to 54 (more accurately, the RDC 24a) are commonly used for the memory cell arrays 22a and 22b, and an RDC 24b is commonly used for memory cell arrays 22c and 22d. For this reason, 8 word lines are selected. In contrast to this, when one word line, e.g., the word line 51, is selected, the three word lines 52 to 54 related to the word line 51 are selected simultaneously with the word line 51. In addition, as shown in FIG. 5, other word lines are not selected at random, and the word lines are selected in units of minimum memory arrays. The memory cell array selected as described above is called an activated memory cell array.
FIG. 6 shows a word line drive circuit including a row decoder (RDC), and FIG. 7 shows the timings of main nodes of the word line drive circuit.
Referring to FIG. 6, a power supply voltage Vcc is applied to the drain and gate of an n-channel MOS transistor (to be referred to as an NMOS hereinafter) 60, and the source of the NMOS 60 is connected to one terminal of a capacitor 61 having a large capacitance. This NMOS 60 is normally set in an ON state, and a potential WBST of the source is set to be the power supply voltage vcc. A row address strobe signal (/RAS) is supplied to a delay circuit 62 obtained by connecting a plurality of inverter circuits in series, and the row address strobe signal is delayed by the delay circuit 62 by a predetermined period of time so as to be output from the delay circuit 62 as a signal XVLD. This signal XVLD is supplied to the other terminal of the capacitor 61, and supplied to the gates of a p-channel MOS transistor (to be referred to as a PMOS hereinafter) 64a and an NMOS 64b through an inverter circuit 63. The PMOS 64a and NMOS 64b constitute an inverter circuit 64.
When the signal XVLD changes from low level to high level, the potential WBST is boosted to a potential higher than the power supply voltage vcc through the capacitor 61, and the PMOS 64a is turned on. For this reason, the boosted potential WBST is applied to each row decoder (RDC) as a word line drive voltage (WDRV). In each row decoder, a word line is selected in accordance with a combination of address signals. The number of word lines selected as described above is the number of word lines determined by the refresh operation described above.
Each row decoder (RDC) is constituted by a NAND circuit 65a for outputting a logic signal in accordance with an internal signal XAj generated in correspondence with an address signal, an inverter circuit 65b, and NMOSs 65c, 65d, and 65e. The NMOS 65d automatically transfers the boosted voltage to a word line WL using capacitive coupling between the gate and channel of the NMOS. The NMOS 65c encloses the potential of a drain node D.
Assume that a failure has occurred due to a certain reason at a portion indicated by reference numeral 80 in the memory cell array 22a shown in FIG. 8, and that a word line is subjected to leakage. This failure can be easily remedied by a redundancy circuit. However, a DRAM is tested in a long cycle, the failure causes a failure bit map indicated by reference numerals 81 to 84. That is, the word lines 82 to 84 selected simultaneously with the word line 81 are regarded as word lines in which failures have occurred.
This is because leakage occurs at the portion 80 in which a failure has occurred and which is shown in FIG. 8. When the long-cycle test is performed, as shown in FIG. 9, the potential of the word line drive voltage (WDRV) is dropped. Therefore, the potential is dropped regardless of charging the capacitor 61, and the word lines selected simultaneously with the word line in which a failure has occurred are damaged to fail.
In this case, the following problem is posed. That is, word lines in which no failure has actually occurred and which are not damaged are remedied by a redundancy circuit together with a word line in which a failure has occurred. For this reason, the word lines which are actually damaged are to be remedied by the redundancy circuit, and the number of damaged word lines may become larger than the number of word lines which can be remedied by the redundancy circuit. In this manner, since products which cannot be remedied are regarded as defective products, a yield is merely decreased.
The number of word lines which can be remedied is as follows. For example, in FIG. 8, it is assumed that one word line in which a failure has occurred can be remedied in each minimum memory cell array MCAmin obtained by dividing a memory cell array with dotted lines. In the semiconductor memory described above, if a failure is present in the word line 82 together with another failure, the minimum memory cell array having the word line 82 cannot be remedied. Therefore, this product is regarded as a defective one.
As described above, in the conventional semiconductor memory apparatus, when a word line is subjected to leakage, and a failure has occurred in the word line due this leakage, a long-cycle test disadvantageously recognizes that failures have occurred in other normal word lines which are selected simultaneously with the word line in which the failure has occurred.